1. Technical Field
Embodiments of the present disclosure relate to a fuse test mode detection device, and more particularly to a technology for improving detection efficiency of a test mode of a fuse.
2. Background Art
A Dynamic Random Access Memory (DRAM) includes a plurality of memory cells arranged in a matrix form.
However, if a defective or failed cell occurs in at least one memory cell from among the plurality of memory cells, it is impossible for a semiconductor memory device to normally operate. Thus, the semiconductor memory device having the defective cell is regarded as a defective product and discarded. Because semiconductor memory devices have been developed to have a higher degree of integration at a higher speed, there is a higher possibility of causing defective cells.
As a result, a production yield is gradually reduced. The production yield is denoted by a ratio of a total number of chips to a number of normal chips. The production yield is needed to determine a production cost of DRAMs.
Therefore, in order to increase the production yield of semiconductor memory devices, many developers and companies are conducting intensive research into a method for fabricating highly-integrated semiconductor memory devices configured to operate at a higher speed and a method for efficiently repairing defective cells.
A widely used method for repairing a defective cell involves embedding a repair circuit configured to replace a defective cell with a redundant cell in the semiconductor memory device.
Generally, the repair circuit includes redundant columns/rows in which redundant memory cells are arranged in rows and columns. The repair circuit selects the redundant column/row as a substitute for the defective column/row.
That is, if a row and/or column address signal for designating a defective cell is input to the repair circuit, the repair circuit selects the redundant column/row instead of the defective column/row of a memory cell bank.
In order to recognize an address for designating a defective cell, the semiconductor memory device includes a plurality of fuses capable of being blown, and the fuses are selectively blown so that an address of the defective cell can be programmed.